Common Drain Amplifier

Note

Work in progress.

Overview

The common drain amplifier is one of three basic FET amplifier configurations. The device is wired so that:

The characteristic property of this configuration is that the amplified voltage gain is close to 1 V/V. This makes it a good voltage buffer or impedance matching device. The common drain amplifier can be used to greatly reduce the impedance of a signal, essentially acting as a Class A Power Amplifier.

A practical MOSFET single-supply design can be seen below. The gate requires biasing in order for the transistor to conduct during the entire input waveform, which is capacitively coupled to the gate. The output is taken through a capacitor from the source.

Generic Design

Generic Design

DC Analysis

The transistor must provide linear operation during the entire signal, so it should stay in saturation mode. The requirements for saturation mode are given by these two equations:

$$V_{DS} \geq V_{GS} - V_t$$ $$V_{GS} \geq V_t$$

As long as this is true, the current through the transistor is given by this equation:

$$I_D = K (V_{GS} - V_t)^2 = K (V_G - V_S - V_t)^2$$

If we take the voltage on the source terminal is developed by source resistor,

$$V_S = I_D R_S$$

And combine it with the current equation, we get either of these nasty quadratics:

$$I_D = K (V_G - I_D R_S - V_t)^2$$ $$V_S = K R_S (V_G - V_S - V_t)^2$$

I will just make some plots to describe the behavior instead of solving. The second equation can be used to model the DC voltage transfer characteristic with $V_S$ being the output and $V_G$ being the input. I will fix $K$ and $V_t$ at $1$ for simplicity and sweep across $R_S$. I’ll also assume that the transistor is in saturation for the input values I’m using.

    using Roots
    using Plots

    Vt = 1;
    K = 1;

    # Logarithmic sweep from 1 milliohm to 10 kiloohms
    RS = logrange(1e-3, 10e3, 8);

    # 3 unknowns that need to be filled
    sweep_gen = RS -> (VG -> (VS -> K * RS * (VG - VS - Vt)^2 - VS));

    # First sweep across RS values
    sweeps = map(sweep_gen, RS);

    # Next, generate solves for gate inputs from Vt to Vt+10 volts.
    solvers = map(sweep -> map(sweep, Vt:(Vt + 10)), sweeps);

    # Finally solve the equations (smaller quadratic solution is the correct one).
    results = map(sweep -> map(solver -> find_zeros(solver, 0:20)[1], sweep), solvers);

    # Plot the results
    plot(title="DC Transfer Function",
        xlabel="Gate voltage (V)",
        ylabel="Source voltage (V)",
        framestyle=:origin,
        xlims=[0, 13.5],
        ylims=[-0.5, 13.5]);
    map((sweep, RS_val) ->
        plot!(Vt:(Vt+10), sweep, label="RS = $(RS_val)", seriestype=:scatter), results, RS);

    # Add "ideal buffer" transfer function
    plot!(x -> x - Vt, label="Ideal Buffer")
DC Voltage Transfer

DC Voltage Transfer

For small resistances less than 1 ohm, this circuit has non-linear behavior, which is not very useful to us. Starting at around 1 ohm, we get an affine function with a slope that starts to approach 1:

$$V_S \approx m (V_G - V_t), \quad m \to 1$$

Small Signal Analysis

Next, we can linearise the circuit to produce a small signal equivalent circuit. For in-band operation, the capacitors are shorted and the model is as follows:

Small Signal Equivalent Circuit

Small Signal Equivalent Circuit

The small signal linearization happens around some DC operating point, which gives us a value for the transconductance $g_m$:

$$g_m = 2 \sqrt{K I_D}$$

Amplifier Gain

The AC input and output points are directly connected to parts of the device:

$$v_g = v_i$$ $$v_s = v_o$$

On the output side, $R_S$ and $R_L$ are in parallel and the current through the combination must equal the dependent source:

$$g_m v_{gs} = \frac{v_s}{R_S \parallel R_L}$$ $$g_m (v_g - v_s) = \frac{v_s}{R_1 \parallel R_L}$$

After substituting we can find the gain:

$$v_i g_m = v_o (\frac{1}{R_S \parallel R_L} + g_m)$$ $$\frac{v_o}{v_i} = \frac{g_m}{g_m + \frac{1}{R_S \parallel R_L}}$$ $$A_v = \frac{g_m (R_S \parallel R_L)}{g_m(R_S \parallel R_L) + 1}$$

If $g_m (R_S \parallel R_L)$ is very large compared to 1, then the amplifier acts like a true buffer.

$$A_v \approx 1$$

Input Impedance

The MOSFET gate is effectively an open circuit for the in-band frequencies. The only path to AC ground is through the biasing resistors.

$$Z_{in} = R_G$$

Output Impedance

We replace the load resistor with a 1 volt test voltage source. Since we disable independent sources in Thevenin analysis, $v_g$ becomes 0 and $v_s$ becomes 1. Thus, $v_{gs}$ is -1. We can see that the dependent source will push current of magnitude $g_m$ from the source to the drain. We can model this as a simple resistor by applying Ohm’s Law:

$$R = \frac{V_{test}}{g_m} = \frac{1}{g_m}$$

This makes the calculation much easier, because now the output side just has two resistors in parallel. Hence, the output impedance is:

$$Z_{out} = R_S \parallel \frac{1}{g_m}$$

Design Trade-offs

Let’s look at all the results we obtained from the AC analysis:

$$g_m = 2 \sqrt{K I_D}$$ $$A_v = \frac{g_m (R_S \parallel R_L)}{g_m (R_S \parallel R_L) + 1}$$ $$Z_{out} = R_S \parallel \frac{1}{g_m}$$

For fairly large loads, this circuit behaves almost perfectly as a voltage buffer. With both $R_S$ and $R_L$ being large, $A_v$ easily approaches one. However, for small loads (such as speakers), the $g_m$ terms would dominate the gain expression. In this case, it’s important to have a large enough $g_m$ to transfer the signal over.

The transistor used should have a large enough $K$ parameter and the DC biasing current should be large enough for $g_m$ to be big. If we have already placed a transistor, we can only control the current that flows through it, therefore this relationship is the most important one:

$$g_m \propto \sqrt{I_D}$$

Increasing $I_D$ makes the buffer better, but it also increases the amount of power wasted as heat through the transistor and the source resistor.

$$P_{waste} = V_{DD} I_D$$ $$P_{waste} \propto I_D$$

The trade-off we have is that increasing the current will improve circuit behavior but reduce power efficiency.

There are two things we can change to alter $I_D$: $V_G$ and $R_S$. We can now derive a optimal performance and optimal efficiency circuit.

Optimal Performance

Optimal Efficiency

Frequency Response

High Frequency Model

The parasitic capacitances present inside the MOSFET device limit the bandwidth of the amplifier. At higher frequencies, we can model the MOSFET with the following circuit:

High Frequency Model

High Frequency Model

The gate-to-drain capacitance is the most significant one for this circuit, since the drain is an AC ground. Together with the gate biasing resistors, it forms a low-pass RC filter with a cutoff frequency of:

$$f_c = \frac{1}{2 \pi R_G c_{gd}}$$

Therefore, gate biasing resistance needs to be small enough for the signal to remain intact.

The gate-to-source capacitance will practically disappear in this configuration, thanks to the Miller Effect. The AC gain of this amplifier is close to 1, therefore:

$$c_M = c_{gs} (1 - A_v) \approx 0$$

The effect of the drain-to-source capacitance depends on the output impedance and is usually negligible. The cutoff frequency of the low-pass RC filter formed here will be at least an order of magnitude larger than the one due to the gate-to-drain capacitance.

For practical designs you will need to find out the gate-to-drain capacitance from the transistor datasheet. It’s usually listed as Reverse Transfer Capacitance.

Low Frequency Model

The coupling capacitors used in the circuit both form high-pass RC filters. These component values should be picked with care to avoid filtering the lower frequencies of the signal.

Low Frequency Model

Low Frequency Model

The gate coupling capacitor forms a high-pass filter with the gate resistance. For source coupling capacitor, the equivalent resistance is given by the $R_L$ in series with the output impedance. Combining the two poles together gives this expression for the cutoff frequency:

$$f_c = \frac{1}{2 \pi \sqrt{R_G (R_L + Z_{out}) C_{C1} C_{C2}}}$$

For practical design, you can make $C_{C1}$ bigger than is usually needed, so that the output pole dominates the frequency response:

$$f_c \approx \frac{1}{2 \pi (R_L + Z_{out}) C_{C2}}$$

Sample Design

Here’s a sample design from my speaker driver project for a 12 volt single supply. This is a audio amplifier which uses the IRF740 power transistor. You can read more about it on the project page.

Sample Design

Sample Design