Frequency Counter

Note

This project is a work-in-progress.

Introduction

A frequency counter is an intrument which is able to numerically display the frequency of an incoming periodic signal. It’s a useful lab device which can be used for tuning oscillators or tracking frequency drift in analog radios.

Unlike spectrum analyzers, which sample incoming signals and compute Fourier transforms, frequency counters are rather rudimentary tools. The incoming signal is clipped and fed into a digital counter, which effectively counts how many peaks are present in the signal during a known timeframe.

System Diagram

The generic system diagram for a frequency counter looks something like this:

Note that this is primarily a digital instrument. The comparator effectively performs a 1-bit analog-to-digital conversion, after which the rest of the signal chain is fully digital.

Rev 1.0 Design

Core Components

The core components around which the rest of the circuit needs to be built around will be the Counter IC and Comparator IC. RF integrated circuits are quite expensive, and my goal is to make something that I can actually afford to make.

After browsing around on Digikey, I picked these high-speed digital ICs to get the job done:

• TLV3603DCKR
• 74VHC4040FT

The TLV3603 is rated to accept inputs up to 325 MHz, which esentially gives us everything before UHF. The 74VHC4040FT will handle inputs up to 210 MHz. In order to avoid the counter from becoming the bottleneck, I’ve implemented 2 bits using 74LVC1G80 D flip-flops. These can handle up to 400 MHz typically and will divide the input signal frequency by 4, meaning that the main counter receives a maximum input signal frequency of 80 MHz.

System Diagram

Expanding on the generic system diagram with specific design details, the Rev 1.0 design looks something like this:

Frontend

The frotnend is the small analog portion of the counter. This part of the circuit accepts the input signal and converts it to a digital waveform.

Maximum Input Power

R201 and R202 provide a 50 ohm termination for the RF input signal. This will minimize reflections and standing waves in the transmission line. The resistors basically act like a dummy load, so I picked 50 ohms, 0.1% tolerance, 0.25 W to get the job done.

D201 and D202 are limiting diodes. They will become a short circuit for voltages above 0.89 V in both directions, which will cause high power signals to be reflected back into the transmitter, protecting our device. Using Ohm’s law, we can find the maximum power before the limiting diodes begin operating.

$$p_{max} = \frac{(v_{rms})^2}{50} = \frac{v^2}{100} = 7.92 \text{ mW} = +9 \text{ dBm}$$

The diode’s maximum power dissipation is 250 mW (+24 dBm). In the worst case of a low-impedance DC source, this is the largest input that can theoretically be handled before there’s internal damage to the device.

With some margins for safety, we can set the maximum input power ratings to be:

• Recommended (low SWR): +6 dBm
• Maximum (low SWR): +9 dBm
• Absolute maximum (high SWR): +20 dBm

These ratings are kind of bad (+6 dBm = 4 mW, this slightly above the level that VNAs operate at), but for now I can add external attenuators to let high power input signals to be measured.

Comparator Input

The comparator should not receive voltages that are 200 mV lower than its negative rail. Since my input is not biased, that means we need to remove the negative peaks. D203 and R203 provide that protection, thanks to the low forward bias voltage of Schottky diodes.

R203 limits the current passing through on the negative cycles, but forms a low-pass filter with the diode junction capacitance, so the value needs to be relatively low. At 470 ohms, the cutoff frequency is around 338 MHz, which is above the maximum input frequency on the comparator.

Theoretical S11

Converting the comparator and diodes into their respective series resistance and capacitance, we can create a linear model for the input network. The Schottky diode has a high junction capacitance, which means the plots looks a bit different in the two cases.

For positive inputs (Schottky is approximated as a capacitor):

For negative inputs (Schottky is approximated as a short circuit):

With a return loss of over -25 dB in the entire band, reflections should be kept under control for the entire band.

Reference Clock

The timebase is implemented using a 32.768 kHz crystal oscillator (similar to the one used in watches).

U301 divides the frequency by a factor of 1024, producing a 32 Hz reference clock. Using the U302 counter, we can generate submultiples up to 0.125 Hz (period of 8s).

All eight reference signals are connected to an 8:1 multiplexer, which is controlled by the on-board microcontroller. The output is used as the variable gate clock for the measurement unit.

The idea is that increasing the frequency gives out faster samples, while decreasing the frequency provides averaging and allows measuring sub-1 Hz signals.

Measurement Unit

Part 1: High Speed Digital

The measurement unit is the core part of the frequency counter. This is the digital logic which counts the peaks detected by the comparator.

U401 implements the timing gate as a NOR gate. Inverting gates are the fastest logic elements and the phase shift does not matter in this application. Next, two D flip-flops are wired in ripple counter configuration to provide frequency division by 4. Since the flip-flops don’t have a Q output, I added in a NOT gate (U403) to sample the stored value.

You might notice that the flip-flops do not have a reset pin. Certainly, I could add lot of extra logic to implement resetting, but a much easier solution to this is making the adjustment in software, based on the last value read from those flip-flops.

There’s one other thing we need to account for. If we trace the clock and signals Q0-2, we see an issue. Note that flip-flops are triggered by a rising clock, but the counter ICs are triggered with a falling clock:

Peak	Q0	Q1	Q2	Counter Value
0	0	0	0	0
1	1	0	0	1
2	0	1	1	6
3	1	1	1	7
4	0	0	1	4
5	1	0	1	5
6	0	1	0	2
7	1	1	0	3
8	0	0	0	8 (with Q3)

When looking at Q3 and above, the count will be correct. The correction that we need to put in is to map 2 <-> 6 and 3 <-> 7 in the bottom 4 bits.

Part 2: The Rest

How many bits do we need to store? The most demanding scenario we can have is a 8 second gate clock with a 325 MHz input signal. This gives us a maximum value that is possible to capture during a single gate cycle: $2.6 \times 10^9$. Using log2 and rounding up, we compute that the smallest count of bits that we need is 32. Each counter IC gives us 12 bits, and the custom high-speed logic gives us another 2 bits. With 3 counter ICs, we have 38 bits to work with.

Serializer

We don’t have a lot of pins on the microcontoller to spare, so we want to pack our 32 counter bits into a single two-wire interface. The serializer is a series of four 8-bit shift registers, which effectively provides a rudimentary SSI into the counter.

Microcontroller

Some of the high speed digital components require a 5V input, which limits the choice of an MCU quite significantly. The ATtiny1634 is a nice choice as it has:

• 5V logic
• Plenty of I/O pins
• Easy in-place programming over SPI
• Access to Arduino libraries and tools

The ISP header allows programming from an external device without removing the MCU from the board. The data lines are nicely protected with resistors, however, the programmer power and board power should to be kept separate. JP601 needs to be pulled out before attaching the ISP programmer and replaced after programming is finished.

Root Page

The root page shows the hierarchical connections between the modules discussed above:

We also have some I/O devices here. I will be using one of those generic SSD1306 0.96 inch displays for outputting the counter data. It’s 4 pin module which is controlled via I2C. The gate clock is controlled using the digital encoder, and the switch is used for controlling the sampling mode. The LEDs are used to communication information about sample/hold behavior.

Power

The counter is designed to be powered with a single LiPo cell. I also added a USB-C charging port.

For the power supply, I copied the TP4057/DW01 circuit that you can find on a bunch of Chinese LiPo charging boards. Additionally, there’s a 5V boost converter with all the stuff it needs. There isn’t much room for creativity here, I literally just followed the datasheet to design this part of the device.

PCB

For the PCB, I went with a four-layer design due to the somewhat higher complexity of the circuit. Honestly, having access to inner power planes did spoil me a bit. The board is almost entirely SMD, except for some capacitors and I/O elements. When I was working on this PCB, I found some test points in my box of spare components and decided to add some to the board (this will turn out to be a really good idea).

Rev 1.0 Testing

The board powered on from battery without any issues right away with the regulator outputting a solid 5 volts. Then, I plugged in the USB cable to make sure that the battery was indeed charging. It worked just as expected, and I will probably keep reusing this battery circuit in many other projects. Here’s a picture much later of the battery getting to full charge:

Next, I took an S11 measurement and was somewhat disappointed with the results:

The reflection was about 10 dB higher than I expected, which might be caused by some mismatch in the line. Nevertheless, the reflections are still decent enough to test the board without having to worry about breaking the equipment.

The other dissapointment was that the reference clock circuit was completely silent. I didn’t research crystal oscillators much before making the board, and unfortunatelly it did not start oscillating at all. I still wanted to test the rest of the circuit, so I decided to inject my reference clock from the outside. I had to fix another two messups:

• The reference clock is not fed into the MCU. I swear I remember adding this trace in the design, but maybe I accidentally deleted it during refactoring. I added a wire from the ref. clock test point to one of the unused MCU pins and everything was fine.
• One of the ICs has an active low enable pin, which I connected to 5V by mistake. I carefully cut the trace with a precision knife and shorted it to a nearby ground pin.

With the function generator hooked up to the SMA input and another function generator producing a reference clock, I measured the DIV4 test point, which shows the gated signal frequency divided by a factor of 4:

That looks almost correct: those solid boxes are actually high frequency square wave oscillators and the gap between them is the modulation from the reference clock. However, the width of the signals concerned me here and later in the testing, I discovered that my clock divider was malfunctioning as well. Tossing the entire reference clock circuit out, I fed my external clock straight into the other test point for further testing.

Now, I moved onto getting the microcontroller working. I used an Arduino Uno (or rather the SparkFun clone) as a programmer for my ATtiny, and after some struggle with the AVR compiler got a bare-metal binary to upload and blink the sample/hold LEDs:

Lastly, I needed to add the I2C display. Once again, I made a mistake by not including pull-up resistors, so I had to hackily solder some on the display pins:

The display powered on and printed out gibberish?

I ran into a very funny issue when trying to write to the display. The SSD1306 accepts the frame data as a 1 kB input over I2C. I was trying to send the entire frame at once, however my MCU would keep crashing.

Everything became clear when I looked at the datasheet and noticed that the ATtiny1634 only has 1 kB of RAM!! The stack would overflow when I allocated a kilobyte buffer and crash the MCU. Splitting the logic into 8 writes of 128 bytes makes the display work as expected.

I created a simple LCD-style font to print out digits and started the real testing.

The counter seemed to work well in the range of 100 kHz - 160 MHz. On the lower side, the frequency would measure higher for some reason. My guess is that it has something to do with the comparator switching very fast, which may be fixable with hysteresis (unfortunatelly that will destroy high frequency performance).

On the higher end, I’m not entirely sure what happened, but I think the Schottky protection diode is to blame. It’s capacitance is very large and it acts like a voltage divider on the comparator input. Redesigning the circuit to include biasing could help, but would harm lower frequency performance.

For my last test of this board, I wanted to plug in a transmitting radio into my counter. I attached a Baofeng tuned to the national calling frequency on low power mode (+27 dBm) through a 20 dB attenuator (+7 dBm) and measured the frequency:

Overall, I’m quite satisfied with the board I made. That being said, I’m certainly making a Rev 2 to fix all the problems and dumb mistakes I made. There are some design choices that should probably be re-examined…

List of Problems

So… this is all the serious problems with the board:

• Reference clock is not connected to the MCU
• The reset pin should not be used as a GPIO
• I2C pull-ups
• 74HC251 needs OE to be LOW to operate
• Time reference oscillator is broken
• Poor performance below 100 kHz
• Poor performance above 160 MHz

And here are some things that would be nice to change:

• The battery terminal should have a proper connector
• The power switch should only have 2 pins
• Power multiplexer to allow USB-C to power the circuit directly
• The programming jumper seems unnecessary

Work-In-Progress

More stuff coming soon…

Notes

• Check out the design on my GitHub